Perception Coprocessors for Embedded Systems

Recognizing speech, gestures, and visual features are important interface capabilities for embedded mobile systems. Perception algorithms have many traits in common with more conventional media processing applications. The primary motivation for this work is that applications such as real-time, speaker-independent, large-vocabulary, domain-independent continuous speech recognition systems require more performance than is currently available on embedded processors. Even on modern highperformance processors the performance is just barely able to keep up with real-time demands while consuming power at a rate that is well beyond what can be sustained on mobile systems. The solution to this dilemma has traditionally been to design a special ASIC. ASIC design however is both expensive and lacks the generality needed to support different phases of a complex algorithm or even evolutionary improvements to base method. This paper introduces an execution cluster based coprocessor architecture and its CMOS implementation. This is compared against software implementations of algorithms running on a general purpose processor and also against custom ASICs. The cluster achieves an order of magnitude improvement in energy consumption over a conventional processor while retaining a reasonable level of generality. The architecture is evaluated on several important perception applications where energy consumption is shown to improve by a factor of 12-55 times and energy-delay product improves by a factor of 3.8 40 times over conventional processor approaches.